Now time to introduce the overall system. Surprisingly I am including a diagram that I drew before I even started writing hardware, and it is still valid.
System Block Diagram
The FPGA is a Virtex 2P, on a Xilinx University eval board. Most of our peripherals are standard (memory, pushbuttons, LEDs, UART) but we also have a custom core which is a controller for the ADC we are using. External to the eval board we have a 6 legged robot with 18 servo motors controlled by an SSC32 servo controller. This communicates with our board via RS232.
We have analog Sharp IR distance sensors, which connect to the ADC128s102. This ADC runs between 8 and 16 MHz (12.5MHz is currently a nice division of our system clock), and has 8 channels. Our custom controller is responsible for providing a clock, clocking select bits in and data bits out, as well as providing a Chip Select signal to control the device's operation.
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