Its simple really. There are 2 reasons.
Reason 1: Here I am, 2 weeks from the end of my FPGA project class and I know that I have to write a final report. And, as all school projects go (for me anyway), most of the work will be done in these next 2 weeks. So I'll document it all, share it with the world, and save myself time later when I am writing the final report.
Reason 2: VHDL takes a long time to synthesize. What better use of that time than to check the news and write blog posts about my robots!
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